RISC-V and machine learning: a survey
Shriman Keshri, Apparna Singh, Chinmaya Kumar Palo, Shreya Adya, Subhankar Mishra
cs.LG · cs.AR
Quick verdict
Broad, current survey unifying RISC-V ML across ISA/cores/toolchains/apps, but internal number conflicts and apples-to-oranges tables weaken comparisons.
Summary
This survey reviews the intersection of the RISC-V instruction set architecture and machine learning, positioning itself as an update to the 2020 survey by Nicholas et al. with a post-2020 emphasis. Using a documented search across six databases with explicit inclusion and exclusion criteria, the authors organize more than 100 contributions into six sections: ISA extensions and nomenclature, academic and commercial core implementations, software frameworks (FPGA flows, TVM/MLIR/Glow/IREE compilation, embedded stacks), applications (medical, robotics, object detection), performance, and security. Headline evidence includes Table 6's comparison of roughly 20 academic cores (VRoom 11.3 DMIPS/MHz, BOOM 3.93, SERV 0.718) and Table 15's unified benchmarking, where reported energy efficiencies range from 290 to 1200 GOP/W and speedups from 2x to 15x. The paper proposes four research directions: specialized neural ISA extensions, adaptive/modular processors, security frameworks, and energy-efficient multi-clock domains. Its main limitations are methodological rather than empirical: the unified tables mix DMIPS and CoreMark metrics, incomparable baselines (ARM Cortex-M4 vs. general RISC-V vs. space-grade), and internal contradictions (XiangShan 2 vs 2.2 GHz; CFU Playground 4.1x vs 55x; HULK-V 6.8x vs 112x); standard Z/Sm extensions are mislabeled as custom in Table 3; no original experiments are conducted.
Review complete
Assessment at a glance
5
risk flags identified
● high 0
● medium 3
● low 2
5 strengths · 5 weaknesses · 5 author questions
AI text signal = Binoculars zero-shot detector score over 20 sampled passages (Fast-DetectGPT co-reported) — absence does not prove human authorship, and a flag does not imply misconduct.
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Key claims under review
- Customized RISC-V ML implementations deliver 2–15x energy-efficiency and 1.5–5x throughput gains over general-purpose RISC-V baselines, concentrated in edge and embedded deployment.
- A cross-stack linkage from ISA extensions through cores, compilers, and frameworks to application outcomes distinguishes this survey from Nicholas et al. (2020), Kalapothas et al., and Agosta et al.
- The RISC-V ML ecosystem comprises 47 distinct processor cores and over 100 research contributions, spanning ultra-low-power IoT parts to emerging server-class and transformer-capable designs.
- Four research directions — specialized neural ISA extensions, adaptive/modular processor architectures, comprehensive security frameworks, and energy-efficient multi-clock domains — address the gaps identified across the surveyed literature.
Strengths
Documented search protocol
Section 1.1 lists six databases (Google Scholar, DBLP, IEEE Xplore, ACM DL, arXiv, Springer), enumerated query strings, and explicit inclusion/exclusion criteria requiring experimental validation and technical depth — more auditable than most surveys in this space.
Genuinely current coverage
Includes 2024–2025 primary works absent from the 2020 baseline: VEXP softmax extensions (ARITH 2025, 162.7x latency), MARVEL auto-generated extensions, the Zabha/Smcdeleg/Smstateen extensions (Table 3), and bendable-substrate RISC-V, filling the post-Nicholas-2020 gap the authors target.
Normalized core tables with per-entry citations
Honest scoping statements
Actionable future directions
Weaknesses
Apples-to-oranges 'unified' benchmarking
Internal numeric contradictions
Taxonomy integrity failure in Table 3
Headline ranking rests on unverified sources
Editorial lapses undermine the promised rigor
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Scope & Claims
This is a peer-reviewed survey (The Journal of Supercomputing, vol. 82, art. 424, 2026) of the RISC-V ISA's role in machine learning, positioned as an update to Nicholas et al. (2020) [40] and set against Kalapothas et al. [41] and Agosta et al. [42]. Coverage spans post-2020 academic and commercial work: ISA extensions and nomenclature (§2), academic cores (Table 6) and commercial cores (§3.1.2), software stacks from FPGA flows to TVM/MLIR/Glow/IREE (§4), and applications in medical, robotics, and object detection (§5), closing with four research directions (§6, Table 20). The abstract and §1.2 claim five contributions: cross-stack linkage, normalized comparison tables, a framework taxonomy, quantitative synthesis, and the four directions. Aggregate claims are "over 100 research contributions" and "47 distinct RISC-V processor cores" (§7). The most concrete evidentiary claims are performance numbers: VRoom 11.3 DMIPS/MHz, BOOM 3.93, DARKSIDE 1200 GOP/W, and derived ranges of 2–15x in energy and 1.5–5x in throughput (§5, Table 15).
The remaining sections cover Methodology Assessment, Statistical Evidence, Results & Reproducibility, Limitations & Risks, and Verdict & Recommendations.
- All 5 strengths & 5 weaknesses, analyzed in detail
- 5 risk flags with severity, section & reviewer questions
- Methods & statistical evidence assessment
- 5 questions a peer reviewer would ask
- Full six-dimension evaluation report & recommendations
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Frequently asked questions
What does the RISC-V and machine learning survey cover?
It is a 2026 survey (The Journal of Supercomputing) covering RISC-V instruction-set extensions, roughly 20 academic plus commercial processor cores, ML software stacks (TVM, MLIR, IREE, Glow, FPGA flows), and applications in medical devices, robotics, and object detection, with emphasis on work published after 2020.
Is RISC-V actually good for machine learning?
According to this survey, RISC-V is strongest for edge and embedded ML inference, where custom ISA extensions and cores report roughly 2–15x energy-efficiency gains over baseline platforms (e.g., XpulpNN vs ARM Cortex-M4, DARKSIDE at ~1200 GOP/W). Server-class and large-language-model support on RISC-V is described as still early.
What four future research directions does the paper propose?
1) Specialized neural-processing ISA extensions (instruction-level NN acceleration), 2) adaptive and modular processor architectures (runtime-tunable parameters vs FPGA reconfiguration), 3) comprehensive security frameworks for open architectures (side-channel resistance for ML), and 4) energy-efficient multi-clock-domain designs for edge AI.
Was this survey peer-reviewed?
Yes — the text states it is the authors' accepted manuscript for The Journal of Supercomputing, vol. 82, no. 8, art. 424, published May 2026 (DOI 10.1007/s11227-026-08463-z); the arXiv posting (2609.20677) is that accepted manuscript.
About this review
This is an AI-generated preliminary review by Evolve.Pub, produced from the openly available text of the paper. It is not peer review and does not represent the authors' views. The canonical record of the paper is at the publisher link above.
- The extracted text truncates Section 3.1.2 (commercial cores), parts of Sections 4.3–4.5 and 5.5 (security), and Tables 7, 11, 12, 18, 19; judgments about those parts are provisional.
- The reference list is cut off mid-entry, so citation quality beyond the visible ~100 entries could not be assessed.
- Figures are assessable only through captions (Figure 1 outline); no visual content was verified.
- Aggregate totals ('47 cores', '100+ contributions') could not be checked against the truncated tables and are flagged rather than judged.
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