PlaceReasoner-Beta: Reasoning-Driven Macro Placement and Benchmarking
Qiufeng Li, Chengxuan Wang, Rongqian Chen, Quan Cheng, Yihui Ren, Chia-Tung Ho, David Z. Pan, Tian Lan, et al.
cs.AI
Quick verdict
VLM multi-agent macro placement + open post-route benchmark; strong routed-PPA gains, but best-of-5 selection and baseline setup issues temper margins.
Summary
The paper presents PlaceReasoner-Beta, a multi-agent framework that reformulates VLSI macro placement as closed-loop reasoning rather than one-shot numerical optimization. A VLM planner generates candidate placements from the floorplan image, macro specifications, and connectivity clusters; a geometric checker enforces legality and placement principles; a physical checker interprets early implementation feedback; and a post-route optimizer refines promising candidates using final PPA and DRC. A shared skill pack translates decisions into OpenROAD commands, with deterministic legalization as a safeguard. The authors also introduce PlaceReasoner-Bench: 16 tasks from eight open-source RTL designs at 1:1 and 2:1 aspect ratios, with fixed floorplans and I/O, built entirely on Yosys, OpenROAD, Nangate45, and FakeRAM 2.0 and scored by routed PPA and DRC. On Claude-Opus-4.8, the system reports the best timing among DRC-clean baselines on all eight square tasks (TNS down 61.2% versus the baseline field), the only evaluated method routing all 16 tasks with at most two DRC violations, and shorter routed wirelength on most designs without optimizing it; ablations show both images and the skill pack matter, especially at 2:1. Limitations: results use best-of-5-run reporting without statistical testing, several baselines appear weakly integrated with the flow, gains shrink on macro-sparse designs, open-weight backbones fail outright on multiple tasks, and the paper's own ablation rows beat the full system on two square tasks and contradict its 'only method' routability claim.
Review complete
Assessment at a glance
5
risk flags identified
● high 1
● medium 3
● low 1
4 strengths · 4 weaknesses · 5 author questions
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Key claims under review
- Verifier-guided multi-agent VLM reasoning outperforms classical macro placers when judged by post-route PPA and DRC rather than pre-route proxy objectives.
- PlaceReasoner-Beta achieves the best routed timing among DRC-clean baselines on all eight 1:1 tasks, reducing TNS by 61.2% versus the four-baseline field, and by 53.0% at 2:1.
- It is claimed to be the only evaluated method routing all 16 benchmark tasks with at most two DRC violations.
- Routed wirelength improves on most designs despite wirelength never being an explicit optimization objective.
- Both visual grounding (floorplan images) and the encoded skill pack contribute measurably, as shown by the CWI and CWS ablations.
Strengths
Post-route, controlled evaluation protocol
The benchmark fixes floorplans and I/O (Sec. 3.3) so methods differ only in macro positions/orientations, and scores routed WNS/TNS/DRC/wirelength instead of HPWL proxies — directly targeting the proxy-vs-quality gap articulated in Sec. 1. Tables 2-3 and 6-7 report failures honestly (GRT-0116, DRT-0073, timeouts, segfault) rather than imputing values, and the non-comparable Qwen3-VL-30B row on ariane133 1:1 (18,166 residual violations) is flagged in the caption.
Fully open toolchain with geometric diversity
Yosys + OpenROAD + Nangate45 + FakeRAM 2.0 (Secs. 3.3, 4) removes commercial-license barriers, and the 2:1 tasks expose routability failure modes invisible at 1:1 — baseline failed routes jump from 4/32 to 10/32 (Sec. 5.1.2), a robustness axis that ChiPBench (single ratio, ~30% utilization, half macro-free) and RTL-MP (commercial 12nm flow) lack.
Cost transparency and informative ablations
Credible qualitative mechanism
Weaknesses
Double best-of selection with no variance reporting
Baseline integration looks misconfigured
Claims contradicted by the paper's own ablation rows
Small, dated benchmark and untested transfer
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Scope & Claims
The paper couples two contributions. PlaceReasoner-Beta (Sec. 3) is a four-agent framework — VLM Planner, Geometric Checker, Physical Checker, Post-route Optimizer — treating macro placement as closed-loop reasoning over floorplan images, structured coordinates, and progressively costlier EDA feedback, with a shared skill pack translating decisions into OpenROAD commands and a force-directed legalizer as deterministic fallback. PlaceReasoner-Bench (Sec. 3.3) provides 16 tasks: 8 open RTL designs (10-133 macros, 14.2-45.6% macro/core area) at 1:1 and 2:1, fixed floorplans and I/O, Yosys synthesis, OpenROAD on Nangate45 with FakeRAM 2.0 macros, scored by routed WNS/TNS, DRC, wirelength, power, area. Headline claims (Abstract, Sec. 5): best routed timing among DRC-clean baselines on all eight square tasks; TNS down 61.2% (1:1) and 53.0% (2:1) against the baseline field; the only method routing all 16 tasks with at most two DRC violations; shorter routed wirelength on most designs despite never optimizing it.
The remaining sections cover Methodology Assessment, Statistical Evidence, Results & Reproducibility, Limitations & Risks, and Verdict & Recommendations.
- All 4 strengths & 4 weaknesses, analyzed in detail
- 5 risk flags with severity, section & reviewer questions
- Methods & statistical evidence assessment
- 5 questions a peer reviewer would ask
- Full six-dimension evaluation report & recommendations
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Frequently asked questions
What is PlaceReasoner-Beta?
It is a multi-agent system that uses vision-language models to perform VLSI macro placement iteratively: a planner generates candidate macro layouts from floorplan images and connectivity information, geometric and physical checkers verify them, and a post-route optimizer refines the best candidates using final PPA and DRC feedback, instead of one-shot numerical optimization.
What is PlaceReasoner-Bench?
An open benchmark of 16 macro-placement tasks from eight open-source RTL designs evaluated at 1:1 and 2:1 aspect ratios, built with Yosys, OpenROAD, the Nangate45 library, and FakeRAM 2.0 memory macros. Floorplans and I/O pins are fixed so methods differ only in macro positions and orientations, and quality is scored by routed PPA and DRC violations rather than pre-route wirelength proxies.
How much better is it than classical placers?
On the paper's benchmark it reports the best routed timing among DRC-clean baselines on all eight square tasks (total negative slack down 61.2% versus the baseline field) and claims to be the only evaluated method routing all 16 tasks with at most two DRC violations. Caveats: results are reported as the best of five runs without statistical tests, some baselines appear weakly integrated, and the paper's own ablations beat the full system on two square tasks.
Does it require a proprietary AI model?
The headline results use the proprietary Claude-Opus-4.8 model. The same agent workflow also runs on open-weight Qwen3-VL-8B/30B models, but those fail outright on several tasks (routing errors or residual violations), so backbone capability substantially affects results; the framework itself is training-free and its rules are inspectable.
About this review
This is an AI-generated preliminary review by Evolve.Pub, produced from the openly available text of the paper. It is not peer review and does not represent the authors' views. The canonical record of the paper is at the publisher link above.
- Figures are available only as captions and OCR fragments; layout-quality judgments (Figs. 4-5, 8-9) rest on the authors' descriptions.
- arXiv v1 carries unresolved ACM template placeholders (CCS terms reading 'Do Not Use This Code'; received dates of 2007/2009), indicating a draft.
- No repository URL for the framework or benchmark appears in the extracted text; openness rests on the claim, not a link.
- Table 7 omits runtime/token entries for the four non-LLM baselines at 2:1, limiting cost comparison at that aspect ratio.
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