NPU Accelerator: Quantized Real-Time Vehicle Detection on PYNQ-Z1 Using FINN
Daniel Gutierrez, Antonio Cuesta, Jorge Fe, Bruno Gutierrez, Rashed Al Koutayni
cs.AR · cs.AI
Quick verdict
LP-YOLO Slim w2a4 @142.86 MHz meets all four KPIs on PYNQ-Z1; credible on-board study, but thin external baselines and key evidence sits in internal reports.
Summary
This paper presents an end-to-end hardware/software co-design study deploying a quantized vehicle detector on the Xilinx Zynq XC7Z020 (PYNQ-Z1) via Brevitas quantization-aware training, QONNX export, FINN dataflow compilation, and Vivado implementation, with all headline numbers from on-board measurements. Four simultaneous requirements define success: >30 FPS, >7 FPS/W, programmable-logic latency <50 ms, and VOC mAP@0.5 >0.55. The authors explore model capacity (YOLOv3-tiny vs. lightweight LP-YOLO/Slim), precision (w4a4, w2a4), input resolution (320/256), FIFO sizing, and PL clock (100-200 MHz). Of the six measured configurations, only LP-YOLO Slim (256x256, w2a4) at 142.86 MHz closes all four KPIs: 35.66 FPS, 12.25 FPS/W, 45.11 ms PL latency, 0.594 VOC mAP; the same model at 125 MHz misses latency by 1.49 ms. Notably, automatic FIFO sizing lifts throughput from 22.15 to 35.00 FPS at 100 MHz, and the paper candidly documents a 38 FPS FINN estimate versus ~22 FPS measured. Main limitations: mAP is missing for several hardware rows; the only mAP-measured LP-YOLO configuration scores 0.390 VOC; accuracy evidence rests on a single corpus with favorably larger boxes (0.492 on filtered COCO); key comparisons (QAT vs PTQ, box statistics) cite unpublished internal reports; and no code or model release is stated.
Review complete
Assessment at a glance
5
risk flags identified
● high 0
● medium 3
● low 2
5 strengths · 5 weaknesses · 5 author questions
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Key claims under review
- LP-YOLO Slim (256x256 input, w2a4) at 142.86 MHz is the only measured configuration meeting all four project KPIs simultaneously: 35.66 FPS, 12.25 FPS/W, 45.11 ms PL latency, and 0.594 VOC mAP@0.5.
- FIFO sizing is a first-order performance lever: FINN automatic sizing roughly doubles throughput versus manual depth-6 at the same 100 MHz clock (22.15 to 35.00 FPS).
- FINN analytical cycle estimates diverge substantially from board measurements (38 FPS estimated vs ~22 FPS measured at 100 MHz), so on-board validation is mandatory for KPI closure.
- Quantization-aware training is required at low bit-widths: at 4-bit, QAT recovers to within ~0.006 mAP@0.5 of the floating-point baseline while PTQ loses ~0.17 mAP (per the project's internal report).
- The VOC-vs-filtered-COCO accuracy gap for the Slim model (0.594 vs 0.492) is partly mechanistic: VOC vehicle boxes are 2-3x larger (median 67.9 vs 21.1 px at 320 px input).
Strengths
Candid three-tier evidence hierarchy
Sec. III-B explicitly separates FINN analytical estimates from board results, documenting a 38 FPS cycle estimate realized as ~22 FPS on board at 100 MHz; Sec. IV-G refuses four-KPI closure for rows lacking mAP (dashes in Table I).
Genuine four-variable hardware ablation with measured deltas
At identical model/precision/clock, automatic FIFO sizing lifts throughput 22.15→35.00 FPS and cuts PL latency 62.41→40.82 ms (Sec. V-A/B, VII-B); the 125→142.86 MHz pair isolates clock scaling (+14% clock → +14.2% FPS, -12.4% latency, +3.9% power, Sec. VII-A).
Mechanistic corpus-gap analysis with own measurements
Negative results retained and useful
Quantified KPI margins in closure table
Weaknesses
Accuracy evidence never tied to most deployed bitstreams
Corpus-dependent KPI closure
No external baseline or prior-art positioning
Single-run measurements, thin margins, no uncertainty
Underspecified evaluation and 'real-time' protocol
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Scope & Claims
The paper reports a hardware/software co-design campaign deploying a quantized vehicle detector on the Zynq XC7Z020 (PYNQ-Z1) via PyTorch → Brevitas QAT → QONNX → FINN → Vivado, with all headline numbers taken from on-board measurements. Success is defined a priori as simultaneous satisfaction of four KPIs (Sec. II-A): >30 FPS, >7 FPS/W, PL latency <50 ms, and VOC mAP@0.5 >0.55. The central claim is that LP-YOLO Slim (256×256 input, w2a4) at 142.86 MHz is the only measured configuration closing all four: 35.66 FPS at 2.91 W (12.25 FPS/W), 45.11 ms PL latency, 0.594 VOC mAP (Table II). Secondary claims: FIFO sizing materially changes throughput; FINN analytical estimates diverge from board results; QAT is necessary at low bit-widths; and the VOC-vs-COCO accuracy gap is mechanistically tied to object size.
The remaining sections cover Methodology Assessment, Statistical Evidence, Results & Reproducibility, Limitations & Risks, and Verdict & Recommendations.
- All 5 strengths & 5 weaknesses, analyzed in detail
- 5 risk flags with severity, section & reviewer questions
- Methods & statistical evidence assessment
- 5 questions a peer reviewer would ask
- Full six-dimension evaluation report & recommendations
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Frequently asked questions
What performance does the final NPU design achieve on the PYNQ-Z1?
LP-YOLO Slim with 256x256 input, w2a4 quantization, and a 142.86 MHz PL clock reaches 35.66 FPS at 2.91 W (12.25 FPS/W) measured on-board with batch 100, with 45.11 ms programmable-logic latency and 49.77 ms end-to-end latency. It is the only configuration in the paper meeting all four project targets (FPS, FPS/W, latency, accuracy) at once.
How accurate is the detector?
It scores 0.594 mAP@0.5 on Pascal VOC, above the project's 0.55 target, and 0.492 on the project's filtered COCO-derived vehicle corpus. The authors attribute part of that gap to VOC vehicle boxes being 2-3x larger. The larger YOLOv3-tiny reference reaches 0.761 VOC but only 12.35 FPS, failing the speed and efficiency targets.
Is the code or the trained models available?
The paper announces no code, model, or dataset release. Key supporting evidence (QAT-vs-PTQ comparison, box-size statistics, BRAM analysis) comes from internal dAIEdge/PYNQ-OPT engineering reports cited as references [1]-[3], which are not indicated as publicly accessible, so independent reproduction is currently difficult.
Why do they use FINN and 2-bit weights instead of a normal YOLO?
The XC7Z020 has only ~4.9 Mbit of on-chip BRAM. Even at 4-bit precision, YOLOv3-tiny weights need ~34.7 Mbit, about seven times too large for a fully on-chip FINN streaming accelerator. Slimming the network to ~0.35 M parameters and 2-bit weights (~1.4 Mbit or less) is what makes an all-on-chip dataflow implementation feasible.
About this review
This is an AI-generated preliminary review by Evolve.Pub, produced from the openly available text of the paper. It is not peer review and does not represent the authors' views. The canonical record of the paper is at the publisher link above.
- Extracted Table I shows five rows while the text discusses six implementations; the 125 MHz Slim row (31.22 FPS, 2.80 W, 51.49 ms PL latency) appears only in prose (Sec. V-C, VI-B) - likely a table extraction gap, all numbers cross-checked against the narrative.
- Figure 1 (workflow) is available only as caption text; no architecture diagrams or resource-utilization tables are analyzable from the extraction.
- References [1]-[3] are internal dAIEdge/PYNQ-OPT engineering reports whose content could not be verified.
- Training/evaluation protocol details (epochs, splits, filtered-COCO definition) are absent from the text, so accuracy numbers cannot be protocol-audited.
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