Fidelity-Aware Scheduling of Quantum Circuits on Multi-QPU Systems
Innocenzo Fulginiti, Antonio Tudisco, Salvatore Zammuto, Patrick Hopf, Deborah Volpe, Helmut Seidl, Giovanna Turvani, Robert Wille, et al.
quant-ph · cs.AI · cs.ET
Quick verdict
GNN predicts pre-compilation fidelity per QPU; tunable scheduler near-matches oracle on emulated 3-QPU setup; gains on ESP proxy, not measured hardware.
Summary
This paper targets device selection in heterogeneous HPC-QC systems, where estimating a circuit's fidelity on every QPU would require k×D expensive compilations. The authors train a GraphSAGE-style GNN on DAG representations of 17,056 MQT Bench circuits (40-dim node features: QASM3 gate one-hot, sin/cos of rotation angles, structural descriptors) to predict the expected post-compilation fidelity—an ESP-style product of calibrated gate success probabilities (Eq. 1)—on three emulated IQM backends: the 53-qubit EQE1 partitioned into 26- and 27-qubit sub-devices, plus the 20-qubit QExa20. A tunable scheduler assigns each circuit by argmax of w·predicted fidelity − (1−w)·load share, interpolating between round-robin and fidelity-first. The model reaches test MAE 1.04%, RMSE 2.00%, and R²≈0.996 (Table IV). On 5,117 test circuits, mean fidelity rises from 0.3436 (round-robin) to 0.3737 at w=1, within 0.0034 of the ground-truth-weighted bound (oracle 0.3759); at w=0.5 it captures 0.3675 with near-balanced load (CV=0.069). Timing analysis shows the prediction path overtakes exhaustive compilation beyond ~35 two-qubit gates (1.72× in the densest bin), though 47% of circuits are individually faster exhaustively and training-label generation amortizes only after ~9.1×10⁴ dispatches. Main limitations: fidelity labels are calibration estimates rather than measured outcomes, evaluation is confined to one technology at D=3, and no repeated training runs or confidence intervals are reported.
Review complete
Assessment at a glance
4
risk flags identified
● high 0
● medium 2
● low 2
5 strengths · 5 weaknesses · 5 author questions
AI text signal = Binoculars zero-shot detector score over 20 sampled passages (Fast-DetectGPT co-reported) — absence does not prove human authorship, and a flag does not imply misconduct.
Levels reflect verification complexity — not a quality score. Evolve never rates your paper.
Key claims under review
- A GNN on uncompiled circuit DAGs predicts post-compilation expected fidelity per QPU with test MAE 1.04% and R²≈0.996 (Table IV).
- The tunable w-scheduler approximates exhaustive fidelity-based assignment: mean fidelity 0.3737 at w=1 vs 0.3759 oracle, within 0.0034 of the ground-truth-weighted bound at every weight (Fig. 8, Table V).
- Intermediate weights buy most of the fidelity gain while keeping devices balanced: at w=0.5, 0.3675 (+7.0% over round-robin) at CV=0.069.
- Prediction-based selection avoids k×D compilations and beats exhaustive selection in wall-clock beyond ~35 two-qubit gates, with savings growing in D (1.72× in the densest bin, Fig. 9).
Strengths
Complete pipeline from prediction to dispatch
Sec. IV integrates DAG encoding, a GNN predictor, and a scheduler with an explicit dispatch loop (Fig. 3); unlike prediction-only device-selection classifiers [14-17], it closes the loop into multi-circuit allocation with a pluggable policy interface.
Unusually candid overhead accounting
Sec. VI-B3/Fig. 9 measure the crossover (~35 two-qubit gates; 110 ms vs 64 ms in the densest bin), admit 47% of circuits are faster exhaustively, account for training-label generation (904.5 s, break-even ~9.1×10⁴ dispatches at D=3), and flag batch-size-one CPU inference as a caveat.
Scheduler analyzed, not just used
Explicit proxy-metric honesty
Strong accuracy across the fidelity range
Weaknesses
Ground truth is itself an estimate
Narrow evaluation scope
No statistical rigor around training
Load model ignores execution cost
Skewed dataset, small attainable band
Full Review Report
$1.99 · one-timeUnlock the complete preliminary analysis Evolve produced for this paper.
Report preview
Scope & Claims
The paper targets workload placement in HPCQC systems: given a batch of k independent circuits and D heterogeneous QPUs, assign each circuit to a device *before* device-specific compilation, maximizing execution fidelity without paying k×D compilations. Three claims: (1) a GNN predicts post-compilation fidelity from the uncompiled circuit with ~1% error (Table IV); (2) a single-parameter scheduler interpolates between round-robin and fidelity-first and approaches exhaustive assignment (Figs. 7–8, Table V); (3) this saves computational resources versus brute-force multi-device compilation (Fig. 9). The scope is deliberately an emulated 3-QPU IQM setting with calibration-derived fidelity (Eq. 1); the authors are explicit that Eq. 1 neglects idle decoherence, crosstalk, drift, and shot noise, and that absolute values should be read as relative indicators (Sec. II-A).
The remaining sections cover Methodology Assessment, Statistical Evidence, Results & Reproducibility, Limitations & Risks, and Verdict & Recommendations.
- All 5 strengths & 5 weaknesses, analyzed in detail
- 4 risk flags with severity, section & reviewer questions
- Methods & statistical evidence assessment
- 5 questions a peer reviewer would ask
- Full six-dimension evaluation report & recommendations
One-time purchase · this paper only
One-time purchase, this paper only. AI-generated preliminary analysis — not peer review.
Frequently asked questions
What problem does this paper solve?
In multi-QPU HPC systems, picking the best device for a quantum circuit normally requires compiling it on every QPU to estimate fidelity, which is expensive. This paper predicts, with a graph neural network, the post-compilation fidelity of a circuit on each QPU before any compilation happens, then schedules whole batches of circuits with a tunable trade-off between fidelity and balanced device usage.
How accurate is the fidelity prediction?
On a held-out test set of 5,117 circuit-device pairs over three emulated IQM devices, the model reports a mean absolute error of 1.04%, RMSE of 2.00%, and R² of about 0.996. Note the prediction target is itself a calibration-data estimate (an estimated success probability), not a hardware measurement.
Is the scheduler actually faster than compiling everywhere?
Only for larger circuits. The prediction path becomes cheaper than exhaustive compilation beyond roughly 35 two-qubit gates (1.72× faster in the densest bin), and the advantage grows with the number of devices. However, 47% of the test circuits were individually faster to compile exhaustively, and the one-off cost of generating training labels amortizes only after about 91,000 dispatched circuits at three devices.
Was it tested on real quantum hardware?
No. Device sizes and calibration data come from real IQM machines at LRZ (EQE1, 53 qubits, and QExa20, 20 qubits), but compilation, fidelity labels, and scheduling were all evaluated in emulation. Hardware validation is explicitly listed as future work.
About this review
This is an AI-generated preliminary review by Evolve.Pub, produced from the openly available text of the paper. It is not peer review and does not represent the authors' views. The canonical record of the paper is at the publisher link above.
- Figures 5–9 were available only as extracted axis labels and captions; visual content (bar heights, bands, scatter spread) could not be inspected beyond the embedded text.
- Supplied metadata lists 8 authors while the extracted title block lists 10 (adding C. B. Mendl and M. Schulz); the discrepancy is in the metadata, not the paper text.
Go deeper on this paper
Wrote a paper? Stress-test it before reviewers do.
Upload your manuscript for the same structured scrutiny — reasoning, statistics, evidence, figures, and reproducibility.