FAME: An FPGA-Based Platform for Approximate Multipliers Evaluation with Pattern-Guided DNN Retraining
Rappy Saha, Nima Amirafshar, Jude Haris, Nima Taherinejad, José Cano
cs.AR · cs.LG · cs.PF
Quick verdict
FPGA replaces LUT emulation for 27 approximate multipliers (3.47x vs CPU) with PatQAT; solid work, though gains rest on weak baselines and only 2 CNNs.
Summary
The paper presents FAME, an FPGA-based platform (Kria KV260) that implements 27 approximate INT8 multipliers — 20 SPRIM8 carry-disregard designs and 7 EVOApprox MUL8S designs — directly in a SECDA-TFLite VMAC accelerator (8 GEMM units), replacing LUT-based CPU/GPU emulation for evaluating accuracy of INT8-quantized DNNs. Alongside, PatQAT retrains ResNet-18 and MobileNetV2 on ImageNet with weights constrained to multiplier-specific 'patterns' (exact-region values plus ±127 from the approximate region) to preserve symmetric INT8 quantization while training on exact FP32 multipliers; a PatProc step later rounds 127-valued weights into the exact region to avoid approximation error during inference. Results: up to 3.47× evaluation speedup versus AdaPT on a CPU with zero emulation overhead (time per image equals exact-multiplier inference, 1.00×), though FAME is 0.75× the raw speed of TFApproxIL on an Orin Nano GPU while offering 4.77× better performance-per-watt; Top-1 accuracy averages 28.9% higher than the TER retraining baseline. Limitations: only two CNNs, a single FPGA board, no variance reporting, PDP compared via a crude 180nm→45nm scaling formula, and MobileNetV2 accuracy collapses for small patterns (ρ4: 23.77%, ρ8: 15.18%) despite PatQAT+PatProc.
Review complete
Assessment at a glance
5
risk flags identified
● high 1
● medium 3
● low 1
4 strengths · 5 weaknesses · 5 author questions
Levels reflect verification complexity — not a quality score. Evolve never rates your paper.
Key claims under review
- Implementing approximate INT8 multipliers directly on FPGA fabric eliminates LUT-emulation overhead, making approximate inference exactly as fast as exact inference (Tax=Tex, 1.00× overhead) and speeding evaluation up to 3.47× versus prior CPU-based emulation.
- PatQAT constrains weights to multiplier-specific patterns that span both exact-region values and ±127, preserving symmetric INT8 quantization, and recovers up to 65.5% more accuracy than the TER retraining approach (28.9% on average across two DNNs).
- Approximate multipliers sharing the same exact region produce identical DNN accuracy under PatProc, and patterns form verifiable hierarchies (ρ1⊂ρ2⊂…) that predict Table III's accuracy groupings.
- FAME is orthogonal to the retraining method: any INT8-QAT TFLite model can be evaluated on AMi8-based accelerators without PatProc or retraining changes.
Strengths
End-to-end real-hardware evaluation instead of simulation
AMi8 Verilog modules are substituted post-HLS into the SECDA-TFLite VMAC (Section IV-B), yielding 27 automated bitstreams (~25 min each) and a full 27-multiplier × 13-pattern accuracy sweep on ImageNet (Table III); Table IV confirms approximate inference costs the same as exact (Tax=Tex, 1.00× overhead), genuinely eliminating LUT emulation rather than merely optimizing it.
Careful attribution of error sources across the pipeline
Figure 4 separates retraining (blue), TFLite INT8 calibration (red arrows: 1.19% ResNet-18, 1.95% MobileNetV2 average loss), and AMi8 deployment (green), so the reader can see the accelerator's isolated effect; the authors also candidly report FAME is 0.75× the speed of TFApproxIL on Orin Nano rather than hiding it.
Principled pattern analysis with explanatory power
Strong reproducibility
Weaknesses
Headline speedup rests on the weakest baseline
PatProc makes retrained inference largely exact, diluting the 'approximate' claim
Method fails for small patterns on compact models
Hardware-efficiency comparison uses a crude cross-node PDP scaling
No variance or uncertainty reporting
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Frequently asked questions
What is the FAME platform?
FAME is an open-source, FPGA-based tool (running on a Kria KV260 board) that implements approximate integer multipliers directly in reconfigurable hardware so researchers can quickly measure how much classification accuracy a quantized deep neural network loses — replacing slow software look-up-table emulation of these multipliers on CPUs and GPUs.
How much faster is FAME than software emulation of approximate multipliers?
Per the paper, FAME is up to 3.47× faster (3.09× on average) than AdaPT running on a desktop CPU, with zero emulation overhead — inference with approximate multipliers costs the same as with exact ones. It is however 0.75× the raw speed of TFApproxIL on an NVIDIA Orin Nano GPU, while delivering about 4.77× better performance per watt.
What is PatQAT and how does it recover accuracy lost to approximate multipliers?
PatQAT (Pattern-guided Quantization-aware Training) retrains a DNN with its weights forced onto a small, multiplier-specific set of INT8 values ('patterns') that includes both error-free values and the symmetric endpoints ±127. Training uses exact multipliers (no emulation), and before inference a rounding step called PatProc maps the ±127 weights into the multiplier's exact region, so approximation errors are largely avoided and accuracy loss shrinks.
Which models, dataset, and multipliers were evaluated?
ResNet-18 and MobileNetV2 on ImageNet (50K test images), across 27 approximate INT8 multipliers: 20 SPRIM8 carry-disregard designs and 7 EVOApprox (MUL8S) designs, evaluated via Top-1 accuracy on an FPGA accelerator and compared against PDP hardware metrics and prior retraining (TER) and emulation (AdaPT, TFApproxIL) methods.
About this review
This is an AI-generated preliminary review by Evolve.Pub, produced from the openly available text of the paper. It is not peer review and does not represent the authors' views. The canonical record of the paper is at the publisher link above.
- Figures 4-6 are described only textually; exact per-point values in those charts could not be verified from the extraction.
- The abstract in the source is truncated mid-sentence; headline numbers were cross-checked against Sections V-C/V-D.
- FPGA resource utilization, timing closure, and measured board power for the accelerator are not present in the extracted text, so hardware-efficiency claims rely on the authors' Table IV figures.
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