EquivSVA: A Formally Verified Dataset of Behavioral Assertions Across Equivalent RTL Implementations
cs.LG
Quick verdict
120-family formally verified RTL assertion dataset; rigorous validation, reproducible artifacts; synthetic origins and single-model demo limits validity.
Summary
The paper introduces EquivSVA, a dataset for studying whether LLM-generated SystemVerilog Assertions capture intended behavior or depend on incidental details of one RTL implementation. Its unit is a behavior family: four structurally distinct but formally equivalent RTL implementations of one machine-readable specification, shared interface-level gold properties, three controlled mutants, and validation evidence. The v2.0 release holds 120 families across 12 control-logic categories (480 RTLs, 914 gold properties, 360 mutants), each passing a fixed 17-job validation suite — RTL equivalence, gold-property proofs, reachability covers, mutant distinguishability, and expected failures on mutants — built on Yosys/SymbiYosys with Bitwuzla and ABC/PDR (2,040/2,040 jobs pass). Family-safe, category-stratified train/dev/test splits (72/24/24) keep all four variants of a family in one split. A demonstration evaluates Qwen2.5-Coder-7B-Instruct (4-bit MLX checkpoint, greedy decoding) on the 24-family test split: 68/96 tasks yield syntactically valid SVA; of 293 interface-only properties, 93 (31.7%) are formally sound; sound-property counts vary across equivalent implementations for 14/24 families; and generated properties detect only 16/279 property–mutant checks (11/72 mutants). Main limitations, acknowledged by the authors: generator-produced variants may share stylistic regularities; coverage is restricted to small control logic; temporal expressiveness is mostly next-cycle implications; and the case study is single-model, descriptive, and quantization-affected.
Review complete
Assessment at a glance
5
risk flags identified
● high 0
● medium 2
● low 3
5 strengths · 5 weaknesses · 5 author questions
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Key claims under review
- EquivSVA provides 120 behavior families in which four structurally distinct RTL implementations are formally equivalent under shared harness assumptions, validated by a fixed 17-job suite with all 2,040 final-family jobs passing.
- Shared interface-level gold properties (914) and three controlled mutants per family (360 total) make implementation sensitivity of assertion generation measurable without changing intended behavior.
- Family-safe, category-stratified train/dev/test splits (72/24/24) prevent equivalent variants of the same behavior from leaking across splits.
- A Qwen2.5-Coder-7B-Instruct case study shows only 93/293 (31.7%) interface-only generated properties are formally sound, soundness varies across equivalent implementations for 14/24 test families, and generated properties detect just 16/279 property-mutant checks.
Strengths
Formal validation is a fully specified, first-class protocol
Every final family passes a fixed 17-job suite (Table 3: 2,040/2,040) covering RTL equivalence (3 jobs), gold-property proofs (4), reachability covers (4), mutant distinguishability (3), and expected gold-property failures on mutants (3), on named open tooling: Yosys/SymbiYosys, Bitwuzla SMT backend, ABC/PDR for multi-register equivalence (Section 5).
The behavior-family abstraction is genuinely novel relative to existing resources
Table 1 positions EquivSVA against VERT, FVEval, AssertionBench, CodeV-SVA, Veri2, and AssertLLM2; equivalence here is an organizing principle (Section 3.1, Eq. 1), extending the author's prior post-hoc transformation study (ref [2]) into a reusable dataset unit with 4 equivalent RTLs + shared gold properties + mutants per family.
Leakage-aware, deterministic evaluation design
Unusually transparent reporting
Internal numerical consistency and complete artifact release
Weaknesses
Synthetic provenance limits the central claim's external validity
Case study is thin, unquantified, and unbaselineed
Soundness metric is conditioned on the evaluator's lowering pipeline
Equivalence and mutant detection are conditional and bounded
Low mutation-detection yield is under-analyzed
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Scope & Claims
EquivSVA (arXiv 2609.26751, cs.LG) is a dataset paper positioned as complementary to VERT, FVEval, AssertionBench, CodeV-SVA, Veri2, and AssertLLM2 (Table 1). It makes three core claims: (1) a reusable behavior-family representation in which four structurally distinct RTL implementations of one machine-readable specification are formally equivalent and share interface-level gold properties plus three controlled mutants (Section 3.1, Eq. 1); (2) dataset-wide formal quality control via a fixed 17-job suite — 3 RTL-equivalence, 4 gold-property proof, 4 cover, 3 mutant-distinguishability, and 3 gold-property-on-mutant jobs per family — with all 2,040 final-family jobs passing (Table 3); and (3) evidence via a single-model case study that assertion quality varies across equivalent implementations (14/24 families, 58.3%, Table 5). The paper explicitly disclaims model rankings and industrial-distribution claims (Sections 3.2, 7, 10), which keeps its claims appropriately scoped.
The remaining sections cover Methodology Assessment, Statistical Evidence, Results & Reproducibility, Limitations & Risks, and Verdict & Recommendations.
- All 5 strengths & 5 weaknesses, analyzed in detail
- 5 risk flags with severity, section & reviewer questions
- Methods & statistical evidence assessment
- 5 questions a peer reviewer would ask
- Full six-dimension evaluation report & recommendations
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Frequently asked questions
What is the EquivSVA dataset?
EquivSVA is a formally validated dataset for SystemVerilog assertion research: 120 behavior families across 12 control-logic categories, each containing four structurally different but formally equivalent RTL implementations, shared interface-level gold assertions (914 total), three controlled mutants (360 total), and per-family formal validation with Yosys/SymbiYosys (a fixed 17-job suite, 2,040/2,040 passing). It ships fixed train/dev/test splits (72/24/24 families) that keep all four variants of a behavior in the same split. Code is Apache-2.0, data CC BY 4.0, released on GitHub with a frozen v2.0 tag.
What did the Qwen2.5-Coder-7B experiment in EquivSVA find?
On the 24-family held-out test split (96 RTL inputs), Qwen2.5-Coder-7B-Instruct (4-bit quantized MLX checkpoint, greedy decoding) produced syntactically valid SVA for 68 of 96 tasks after normalization. Of 293 generated properties that referenced only interface signals, 93 (31.7%) were formally proven sound on their source RTL. For 14 of 24 families, the number of sound properties differed across the four equivalent implementations, and the generated assertions detected only 16 of 279 property-mutant checks, covering 11 of 72 unique mutants. The authors present this as a demonstration, not a leaderboard.
How is EquivSVA different from AssertionBench or Veri2?
Those resources organize individual designs or quality-filtered RTL-assertion pairs. EquivSVA instead groups, per behavior, four formally equivalent RTL implementations together with shared gold assertions and labeled mutants, so researchers can measure whether an assertion generator is sensitive to implementation style while intended behavior stays fixed. It is complementary rather than superior: smaller and fully synthetic, but with per-family equivalence proofs, reachability covers, and mutant checks enforced for every family.
Is EquivSVA based on real industrial RTL code?
No. All families are programmatically generated from machine-readable specifications, which enables exact formal validation but means the dataset lacks industrial naming conventions, structural complexity, and specification ambiguity. It covers small control logic (FSMs, counters, FIFOs, handshakes, timers, arbiters, etc.), and 783 of its 914 properties are next-cycle implications with 131 invariants; the authors list these as explicit limitations.
About this review
This is an AI-generated preliminary review by Evolve.Pub, produced from the openly available text of the paper. It is not peer review and does not represent the authors' views. The canonical record of the paper is at the publisher link above.
- Figures 1-2 are available only as captions in the extracted text; no visual content was analyzed.
- Solver parameters (BMC bounds, timeouts, whether equivalence proofs are unbounded) are not stated in the paper text; judgments about proof strength are provisional.
- References [5], [15], and [16] are 2026 preprints/repository citations that could not be cross-checked here.
- The extracted text appears complete (all sections, tables, and appendix present), supporting high confidence in this review.
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