Circuit-MLLM: Topological Logic-Guided Latent-Space Visual Reasoning for Circuit Schematic Understanding
Jinyuan Deng, Yuqi Jiang, Wenjing Huang, Xin Li, Qi Sun, Cheng Zhuo
cs.CV · cs.AI · cs.LG
Quick verdict
Topology-ordered latent visual reasoning for circuit schematics; big gains on a self-built bench, but single-run evals and inconsistent tables temper claims.
Summary
The paper introduces Circuit-MLLM, a 7B multimodal framework built on Qwen2.5-VL that reformulates circuit schematic analysis as latent-space reasoning. Two components are proposed: (1) a circuit knowledge mining mechanism that fuses features from three vision experts (HAWP, DeepLSD, DINOv2) with the visual tokens during training, and (2) a topology-guided sequencing strategy that orders latent target vectors by a BFS-derived Topological Logic Mask rather than raster scan, supervised with a cosine alignment loss. The authors also construct a 12,000-schematic corpus and Circuit-MLLM-Bench (1,000 schematics, 5,000 QA pairs, five tasks) via an automated YOLO11+OCR+pixel-tracking annotation pipeline with expert verification. On this benchmark the model averages 76.20 versus 61.35 for GPT-5.1 and 48.28 for its Qwen2.5-VL-7B backbone, and outperforms fine-tuned latent baselines Mirage and ILVR on topology tasks (72.26 vs 69.82/68.37). Limitations: all evaluations are single-run without variance or significance tests; the headline comparison pits an in-domain fine-tuned model against zero-shot closed-source models; the expert ablation (Table 5) reproduces the latent-size-4 numbers despite claiming latent size 6; and gains over a simple Textual CoT prompt are only about 1.5 points.
Review complete
Assessment at a glance
5
risk flags identified
● high 1
● medium 3
● low 1
5 strengths · 5 weaknesses · 5 author questions
Levels reflect verification complexity — not a quality score. Evolve never rates your paper.
Key claims under review
- A circuit knowledge mining mechanism internalizes HAWP/DeepLSD/DINOv2 expert features into the latent space during training without any inference-time overhead (Sec. 3.1).
- Ordering latent target vectors by a BFS-derived Topological Logic Mask makes latent reasoning follow circuit topology, beating raster-order latent baselines Mirage (69.82) and ILVR (68.37) with 72.26 average on topology tasks (Table 2).
- Circuit-MLLM reaches 76.20 average on Circuit-MLLM-Bench, 24.2% above GPT-5.1 (61.35) and 57.8% above its Qwen2.5-VL-7B backbone (48.28) (Table 1).
- Latent heatmaps show attention shifting from root component along wires to target device across successive latent pads, mirroring human engineers' tracing workflow (Figs. 5-6).
- The two components are complementary, jointly lifting the topology-task average from 69.85 to 72.26 (Table 3).
Strengths
Novel supervision signal for latent reasoning
The BFS-derived Topological Logic Mask (Eq. 4) and monotone permutation of patch features (Sec. 3.2) is a concrete, well-formulated way to decouple latent reasoning order from raster scan — a genuinely new angle vs. LVR/Mirage/ILVR.
Training-time expert internalization without inference cost
Sec. 3.1 fuses HAWP/DeepLSD/DINOv2 features into visual tokens only during training, sidestepping the error propagation of tool-augmented pipelines like Masala-CHAI; the claim of zero inference overhead is architecturally plausible.
Broad and mostly fair baseline grid
Large-scale automated annotation pipeline
Honest external-benchmark negatives
Weaknesses
No statistical rigor anywhere
Uneven headline comparison
Internal table inconsistencies
Thin benchmark validation
Possible baseline contamination and weak hard-case performance
Full Review Report
$1.99 · one-timeUnlock the complete preliminary analysis Evolve produced for this paper.
Report preview
Scope & Claims
Circuit-MLLM (arXiv 2609.15668, Zhejiang University) targets circuit-schematic understanding with a 7B multimodal model (Qwen2.5-VL backbone) that reasons in latent space along circuit topology rather than raster-scan order. The paper claims three contributions: (1) a Latent-Space Circuit Knowledge Mining mechanism internalizing three vision experts (HAWP, DeepLSD, DINOv2) at training time with no inference overhead; (2) a Topology-Guided Sequencing strategy ordering latent target vectors by BFS distance from a root component (Eq. 4); (3) a 12,000-schematic corpus plus Circuit-MLLM-Bench (1,000 schematics, 1,000 QA per task, five tasks). Headline numbers: 76.20 average on Circuit-MLLM-Bench vs 61.35 for GPT-5.1 (+24.2% relative, advertised as 25%), +57.8% over its own backbone (48.28), and up to +26% over latent baselines on the hardest topology setting (Conn. Ident. Hard EMR 28.52 vs ILVR 22.68).
The remaining sections cover Methodology Assessment, Statistical Evidence, Results & Reproducibility, Limitations & Risks, and Verdict & Recommendations.
- All 5 strengths & 5 weaknesses, analyzed in detail
- 5 risk flags with severity, section & reviewer questions
- Methods & statistical evidence assessment
- 5 questions a peer reviewer would ask
- Full six-dimension evaluation report & recommendations
One-time purchase · this paper only
One-time purchase, this paper only. AI-generated preliminary analysis — not peer review.
Frequently asked questions
What is Circuit-MLLM and what does it do?
A 7-billion-parameter multimodal LLM, built on Qwen2.5-VL, that answers questions about electronic circuit schematics (connections, component counts, component classes) by reasoning in the model's latent space along the circuit's topological order — root component, connecting wires, target component — instead of the usual left-to-right raster scanning of the image.
How much better is Circuit-MLLM than GPT-5.1?
On the authors' Circuit-MLLM-Bench (5,000 QA pairs over 1,000 schematics) it averages 76.20 versus GPT-5.1's 61.35, about 24% relative. The comparison is uneven though: Circuit-MLLM was fine-tuned on 5,000 in-distribution QA pairs while GPT-5.1 was evaluated zero-shot. On the external AMSBench the gap narrows, and GPT-5.1 wins on total-count error (MSE 17.96 vs 38.28).
Is the code or dataset available?
The paper states code is available at github.com/IC-Yuan/Circuit-MLLM. The reviewed text contains no explicit commitment to release the 12,000-image training corpus, the annotation pipeline, or the benchmark itself.
What are the paper's main weaknesses?
Single-run experiments with no variance or significance tests (several ablation gains are under 1 point), a self-built benchmark with unquantified label noise, a headline comparison of a fine-tuned model against zero-shot closed-source models, and internal inconsistencies such as Table 5 reporting latent-size-4 numbers while claiming latent size 6.
About this review
This is an AI-generated preliminary review by Evolve.Pub, produced from the openly available text of the paper. It is not peer review and does not represent the authors' views. The canonical record of the paper is at the publisher link above.
- Figures 1-11 are not analyzable from the extracted text; the qualitative attention-flow claims motivating the method (Figs. 3, 5, 6) and the cropping failure examples (Fig. 7) rest on images that could not be inspected.
- Benchmark construction details are said to be in supplementary material; appendices A-C are included but the promised construction procedures are only partially covered.
- The GitHub repository contents were not inspected, so the actual release status of code, dataset and benchmark is unverified.
Go deeper on this paper
Wrote a paper? Stress-test it before reviewers do.
Upload your manuscript for the same structured scrutiny — reasoning, statistics, evidence, figures, and reproducibility.