Ramesh Nampelly

Research profile

Research summary

Ramesh Nampelly is an early-stage researcher in machine-learning systems whose cataloged work concentrates on the engineering of LLM inference and serving. All three papers reviewed by Evolve, posted to arXiv in 2026, place him in the last author position — a pattern consistent with a senior or supervisory role within a small, stable team of five recurring coauthors (Srikanta Datta Tumkur, Jay Iyer, Mehar Simhadri, Sai Pavan Kumar, Sai Kapil Kumar). The three studies attack the same problem from complementary angles: an atlas measuring 54 Qwen2.5-7B configurations across three GPUs to map which optimizations dominate the cost-quality-latency frontier; a simulation of KV-cache placement across GPU, CPU, and SSD showing that a 73× long-session gain comes from raw capacity rather than placement policy; and a measured study of learned request routing for disaggregated serving in which a calibrated router reaches 0.864 goodput versus 0.835–0.847 for alternatives on eight A40 GPUs. Evolve rates all three papers medium on reproducibility (mean 55/100) and repeatedly credits their candor while flagging small scale, reliance on simulation, and missing significance testing. The bibliographic focus index is 0 because output splits evenly — roughly one third each — across three closely related LLM-serving subfield labels. Citation-based output, impact, and activity axes remain uncomputed for now.

Research keywords

Highlights

• Mapping the cost-quality-latency frontier of LLM inference optimizations

  Last-authored an inference engineering atlas measuring 54 Qwen2.5-7B anchors across 3 GPUs to rank quantization (AWQ, FP8), KV-cache compression, and speculative decoding. Evolve calls it candid and useful, but notes the frontier rests on unvalidated simulation.

• KV-cache tiering gains come from capacity, not placement policy

  A simulation of KV-cache placement across GPU, CPU, and SSD for long-lived sessions shows the headline 73× session gain is a pure capacity effect, while predicted-reuse and prefetch recommendations failed under test. Evolve credits the honesty but limits scope to batch-one simulation.

• Calibrated learned routing tops goodput in disaggregated serving

  On an 8×A40 testbed, a calibrated learned router reaches 0.864 goodput versus 0.835–0.847 for alternatives in disaggregated LLM serving. Evolve calls it a credible hardware study but flags small scale, 3 traces, and no significance tests.

Timeline

1. 2026Posted 'The Inference Engineering Pareto Atlas', measuring 54 Qwen2.5-7B anchors on 3 GPUs to map which optimizations dominate the cost, quality, and latency frontier.
2. 2026Posted 'Where Should the KV Cache Live?', a GPU–CPU–SSD placement simulation showing that the 73× long-session gain comes from capacity rather than policy.
3. 2026Posted 'Calibrate, Then Route', a measured study of learned request routing for disaggregated LLM serving, with the calibrated router topping goodput on 8 A40 GPUs.

Papers in the Evolve catalog

• 2026-09-17

  The Inference Engineering Pareto Atlas: Which Optimizations Dominate the Cost, Quality, and Latency Frontier?

• 2026-09-14

  Where Should the KV Cache Live? Placement Policies Across GPU, CPU, and SSD for Long-Lived Sessions

• 2026-09-14

  Calibrate, Then Route: A Measured Study of Learned Request Routing for Disaggregated LLM Serving

Frequent co-authors