Aditya Pola

Research profile

Research summary

Aditya Pola is an early-stage machine learning researcher at the Indian Institute of Technology Hyderabad, India; this profile is name-resolved from public OpenAlex bibliographic data. The catalog records two first-authored 2026 arXiv preprints sitting in two distinct subfields that split the field distribution 50/50: Merge++ (model merging), which refines merged models through data-free checkpoint inversion and distillation over task vectors, and ISA-Bench (LLM code generation evaluation), a benchmark of 92 computational-reasoning tasks across 5 instruction set architectures with a novel reasoning-execution-gap (REG) analysis. OpenAlex indexes 4 works in the recent three-year window — 1 in 2025 and 3 in 2026 — with h-index 1 and i10-index 0, a very young record in which citation impact has not yet accumulated. Topic profiles cluster around advanced neural network applications and explainable AI, alongside topic modeling, logic and type systems, and NLP techniques. The recorded collaborator pool is small (2 distinct coauthors), anchored by Vineeth N. Balasubramanian and Arkaprava Majumdar. Evolve's reproducibility mean across the two assessed papers is 55, with both rated medium readiness; reviews note missing variance, cost, and loss-ablation reporting in Merge++ and an unvalidated GPT-5.5 judge behind ISA-Bench's REG analysis. This is an early-stage profile bounded by the supplied snapshot.

Research keywords

Highlights

• Merge++: data-free checkpoint inversion to refine model merges

  First-authored 2026 arXiv preprint proposing Merge++, which refines model merges via data-free checkpoint inversion and distillation built on DeepInversion-style inversion of task vectors under task arithmetic. Evolve's verdict: broad gains look real, but the paper reports no variance, cost, or loss-ablation evidence; reproducibility readiness is rated medium.

• ISA-Bench: 92 computational-reasoning tasks across 5 instruction set architectures

  First-authored 2026 arXiv benchmark covering 92 tasks over 5 unfamiliar instruction set architectures, targeting computational reasoning in LLM code generation. Evolve finds careful benchmark construction and a promising novel REG analysis, but one that rests on an unvalidated GPT-5.5 judge; reproducibility readiness is medium.

• Reasoning-execution gap analysis for assembly-level code generation

  Within ISA-Bench, the REG (reasoning-execution gap) analysis is flagged by Evolve as the paper's most promising novelty, probing where LLM reasoning diverges from execution behavior across instruction set architectures; its evidential weight currently depends on an unvalidated GPT-5.5 judge.

Timeline

1. 2025First indexed appearance in OpenAlex yearly counts, with 1 work recorded in 2025.
2. 2026Output accelerates: OpenAlex records 3 works in 2026, up from 1 in 2025.
3. 2026Posts Merge++ on arXiv as first author, introducing data-free checkpoint inversion for merge refinement.
4. 2026Posts ISA-Bench on arXiv as first author, a 92-task computational-reasoning benchmark spanning 5 instruction set architectures.

Papers in the Evolve catalog

• 2026-09-19first author

  Merge++: Universal Merge Refinement Through Data-Free Checkpoint Inversion

• 2026-09-19first author

  ISA-Bench: A Benchmark for Computational Reasoning Across Instruction Set Architectures

Frequent co-authors